1. Field of Invention
The present invention relates to a method for fabricating a read-only memory (ROM). More particularly, the present invention relates to a method for fabricating a nitride read-only memory (NROM).
2. Description of Related Art
In a method for fabricating an NROM cell in the prior art, a stacked ONO layer is formed on a substrate and then patterned to expose a portion of the substrate. A first oxidation process is then conducted to form a buried drain (BD) oxide layer on the exposed substrate. A first implantation is performed to form a buried bit line in the substrate under the BD oxide layer. A second implantation is performed to form a junction region in the substrate around the joint of the patterned ONO layer and the BD oxide layer, and then a polysilicon word line is formed on the substrate crossing over the stacked ONO layer. Generally, the fabrication of NROM cells is integrated with those of periphery devices, wherein a second oxidation process is conducted after the second implantation to form gate oxide in the periphery circuit region.
In the prior art, the BD oxide layer and the gate oxide layer both are formed either by using wet oxidation or by using dry oxidation. However, when dry oxidation is used to form the BD oxide layer and the gate oxide layer, the integrity of the BD oxide layer is lower. When wet oxidation is used, the dopants in the gates of the MOS transistors in the periphery circuit region easily diffuse into the under channels since the gate oxide layer formed thereby has a higher porosity. Therefore, the dopant concentrations in the channels are compensated, and the threshold voltage of the channel shifts correspondingly.
Accordingly, this invention provides a method for fabricating a nitride read-only memory (NROM) to improve the integrity of the BD oxide layer.
This invention also provides a method for fabricating an NROM to maintain the dopant concentrations in the channels of the MOS transistors in the periphery circuit region, so as to prevent the threshold voltages of the MOS transistors from shifting.
A method for fabricating a NROM of this invention comprises the following steps. A stacked nitride layer is formed on a substrate and then patterned to expose a portion of the substrate. An implantation is performed to form a buried bit line in the exposed substrate, and a buried drain (BD) oxide layer is formed on the buried bit line by using wet oxidation. A tilt implantation is then performed to form a junction region in the substrate around the joint of the stacked nitride layer and the BD oxide layer. Thereafter, a gate oxide layer is formed on a periphery device region by using dry oxidation. A polycide layer, which consists of a polysilicon layer and a metal silicide layer, is formed on the substrate covering the stacked nitride layer and then patterned into a word line and a gate of the periphery device.
In another method for fabricating an NROM of this invention, the step of patterning the stacked nitride layer is stopped as a bottom layer of the stacked nitride layer is exposed. The exposed bottom layer is not removed until the bit line implantation is finished in order to avoid channeling effect during the bit line implantation.
In this invention, the BD oxide layer is formed on the buried bit line by using wet oxidation, so the integrity of the BD oxide layer can be improved. Meanwhile, the gate oxide layer is formed on the substrate by using dry oxidation, so the dopant concentrations in the channels of the MOS transistors in the periphery circuit region are not changed, and the threshold voltages of the MOS transistors do not shift. Besides, if the bottom layer of the stacked nitride layer is not patterned until the bit line implantation is finished, channeling effect can be avoided during the bit line implantation.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.